[![English Jobs Logo](/public/img/logo100.png "English Jobs Logo") ### ENGLISH JOBS BELGIUM](/) [post a job](/publish-job) search # 2640 design English-speaking jobs in Belgium Include languages [+]sorted by: relevance · [newest](/jobs/design?sort=date) ### Note Some links might not work from outside the European Union. Dismiss [### Senior Digital *Design* Engineer](/clickout/359e4c4f174085ff?ql=q&sig=583befde9402fbb52769d21e2bf91aad279e576b&e=mTt3kNMoenHdz2FXUNl9NmrfoxJyXhouWCCgHqhrAu8R6bSNzJUrECe6wLNHXDjKFW2XfC_fH1yewVavrksldvQP5DpfXNKBRP-CJv3eRuMbkTC6wj-9ZbU04nByJDPFx1hX6BVwJVYrwC_o1GZLBwggKg18yvG0VW_OFR4NW-x42lN9PvqdzLC5s72C4YDq5sxLxzw73I-dHws5NlcGR0XAXI_mLzchRyWI0WiJvUyS8_Sa58tDYpzb0eGgxQQhrenERxAcg-Wfi-i1vmEGP548AXKrBDX2Ie5BmvUsmn2BMnZr1-cPq0zEECITV6Ch_pszm23cWWXtP66aXsUbDO7KD6iOo_AkA5rd5kvntAlmdSc02s7VhjWmVJkrDJXC0ig22hbET0AXoZsrDzsOBZdJLsL58_ZKMhPjqDvDrD97gmqwC8eJmqyQgJGEL8KuHTZuFpaPXMOAiPOxCZ42by7rtus-euOcwgohQq-je4EcKuSBomP18PgMj5DQ9jSW2Qe93fcqWaacmpJYkMZvyEm9E0f3BqZnPVT-lAfQuvHuGq_1h0cePEyAXPsoKlFklqdZgNLAixMHL83VMSo6euTh5D6UodE8B63L16j4zL3FKPl7M9vxXvsvoHarr3xvy44JboLeBVkF35ApTjC5zioZ1PuOR1AC1pSqwB_zcq-TCcZwiqDwa270gC8ZZIXUIGlcfeZ-xA-w9zRk8QtMMCXd1LeJUUPesNwFrBaslI6QE7q2vX_sSOVUWn-703UgHsEmyTEKM3c_uHpJy5goigPNP5MWoBRAOe2dUI81Wfp8kch9HDk8iKDWy-YsPI0EVHzehX7PmzKsXh_8XXS1KzUuKq9N7GGEY7UTZ18W8UWDqvFJvPIcly1rKduED-vHlTjWfj_jeaaKRMBu9QnDv7JIgyyX3wFzWtoW7zoLviRi_Uk3wnAuYbypki392VVC4YClm9oo_RI8krLyPf-zvIXricykBlBVVu0JJvVSrpbv7MOH0s3mjteAc3Rs7FbXRUBqQf9BvF2u9YHKRTMdf1pFp731h-J85oD06H9YMVXjxqsRAmH1NoEnq2zVdq-Nmu976T7H3-zoz8-uXMvN4qcRy7lFz-yGTKM6Z8qPwD3kNQlpqKwEG192AsPr1ZQqhKvgand8Ik-FSpAjLMxgQkEvYSTbS2tg_PSDlWrd0N6HghjIxLYF1OEzg008kktBtl05dGNV-mCOYzuVDAxCLsJjwMAKCqI6_i-Kq5rRmfWisDUs68wF0SjmxqEg8tqhFBYLfqfBp-gao0W5NHI5FELs296X59o9_3L8w8sgrgLRKS-GCbzqkQ7hCfWR-jjjESSpUHLPQYV_Ru7wWAjVYxOFxuxHDcsbhwnaSZcHgfQ2FMxQDFn6vwCiTJ3jtYlkxXJGM0qrvquAtyKIP8F8&prev=RQ2398D7B05A4137&p=1&pg=6) * ICsense * Arlon * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/fe17aa1498f36ca5?ql=q&sig=b8b75721f347877ef2d78f676001a50fb8dedf57&e=fNjVOYI90HSkmQCAtp7eQjME014XD-DLXe-DNc_aBlYOLJ5SRITAW5IMK3HOe4YZ-YHba2p7D5jnNy3t4cpr5WBihaeYPbH4AZCHb6rsCe9D3ho9FoyVFM0Rqhlfw81c1sdoPr0dvZ3XEPtVaaQaw4IpBHZsryd85PEUTpiy0LO8DIy02is_mccFzphykAHfZJvjhcDlcvOPHR8ivhPI94NPLCi4F4ek_pgfvKwVmzAQYUom9xAqixQPgZziyD3Rot90bI0s41hHpTF3_xUeROpyk46CIGH3-F408USTVnwh5rAC7cXaxFituCz3N0-zTgV2RAwSl6gf3rFu5WMxag9zGSnYM-XsnyUBPJFa_PXRJPsuHSfd2lEPGbJsIjg5zWTJcu1t4yq_NPr72NlyqzYKdJz5uFISuA0CwP8UjM6SJh8faxptIXU5H2igcWl4q1MAPc02o7EYW89eqvVVU2Atw7DVL84k7dcSCbPiqQjTyMqwGRxyVhvi-WepbFHKTT5PEKuK1a1yC6fAYoWxYz4x0pYhx0qVwIEv98XAZjIGPSVBHO9561rJzdfCZZkWcg2FQ3uXVPquPamzJODCW6kieYUQg6Br_IZyTiE2PRYow0UhUxhpVSxJ5HVIuv3x_Hn0mfAM82YO0t777wWff4hX2WuuY4TD5PUI-J5qi6ww5OW4nmzpRZmrFf0caaEmbgE0NAbCr0jfuQBe9jsrea74oJsZHaws7AMYVa1zL0a9Bt9eg5XDsHaWCs9rHck21JB16LpTNj7I8sWfaJOKsmq_gI1x7TwzzZ4q3Ho3elPVo9qqm3MYXfSe3Pc7melI_np96JICenpXBRzOkHZWEaMhgKKSFvWUWULQT4tkdHdh6r-9Dk5BiOXmrj5MRCg9YkXmv0v2o2QWel545ry9Z8Bq6NyS73kof1QbnTPVAZjekMDxbzTY0cH413OF7SOD49TS3FQvVoJ06VLrQ1oqtN6UFiGVrv9lszGD3wg38B_RNBdrTE2C6gLFUsFnfM8PR_WGWH30amFdJWW9qGFMsQSvcxaPdYc29IyYU-xSUWYNEji2jlOLpCHLmy2foMVZWtiSMDNPjJWhJ7tADXD4HDE9YmbaI_1FklLhBQxG9hqNa44kXmGxbSpABKearMUxFsIPdFZ1DXmnvd2LITDj_PxlfY9vC66wyZlsM_3YhPQEdURYj7bajHLDCt4EMxWtN7zzaCsjtYfzzUJoqGMriR1ZUiJOrZxH2ymLGr-cWnvDl56_pNIKaqvnQH3JToh1kTyD__GkXJUxmC8lUHWtdAj4spIoCq3ed9iSzrWhYRw9VbzOR9CtuQDZYmDTxTSTBCFIoZyGdRgcn52xk6bX6DMoihLN8teh5fYTrKu9az0L_f7Qw929bXiuIukHHsdnsOxsvRTCNSl9Lb87HBvFrG_54Q&prev=RQ2398D7B05A4137&p=2&pg=6) * ICsense * Kortrijk * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/8e65f0c1f9f50eac?ql=q&sig=59870de17d14537d705605367c04376a33a92bcf&e=yw2LmcItkYa_VC9xMbGKryhxS1uly6RKqhJ6oiJS8nySsSX1HMr8Gww1cLKr7noNqiVCMxBM4oBgFm2SjPkWTWKlsWAC6xndNPMTcLYM4gawQkFqDgueoH1YB37X_buCXiscjLkGNJ3fipTz36KeVZ4ieP3wIYEfrcsPhZ5UR45J_Dc-xJyomQKMBY5xkqOpnNmg8_xCIwMGqOCGhcuxIbo0-o3V34WKTEhbsrgd0vP9xXxeWY60z_Oib4ZFALZbLlomXuQkD8_h3NOcAcDsFnFpevkyqIhaFM-p9Uf4ou0mc7c7N8iHdWgR6YKf-E6CVMOMb1Tzdz9HkiCZLwCWaGcgPO3ACG3ECBQcvDEBjHeZ-5aZ3bCr9PVhw4ueC2rC5alGTYdAHgkfMeFJlwuFf_LhxpprVeZjgJhafiwqaV9kGIH-wwVdHKvugz4VJ8_z_U3gwnrQ9ZbUbcMOMjJdSCaUVcfB-iLC2FNGwRjfrz3S4giePiGdUCSkjCTh2W4UMPXhOzI76O0kJ9AuIiKCczyCXLmhhSqFqbOYVHKZJ9vYLAVaTDzyKSv5iwLCJXxewWKr56MDtJHJGksKD9N_SAp7Kc3VzVpC0SHC3ZaYTvmwuuwiQFwXNoKV72oyd8QS4y8CN5dm2kpGDOB2wjKSOihkQXOQ3SlIL828X3ZqASRzZcd1_s9oGRvPSVMCH-96GEefuZCGoiVz2YEmFE8U2OIboZnls3ELnj1HkjUcqHLYK18wcJnqgARzR0liHuJmTgolyRnvb6tc5AAcV5YcpT4ePcWk5O2pZFLi6y5OWNsOD5bowP-ydbtM_ZDXtLy8YgxRPzb1WrJmyoKmgss1ojpHPtiSHr3_usBLp-ePOpaxe5XuvBhThEOYJMZuFb1Rzsy2prjVoyfkN1WYvUlRWqnBhIoC6hFaFS2pxoqzGxD4RMkVmSyu8EGW68AVyxIsFSsW8vdFxH1SgFUqmSOp0MYgizzuB2jAamgPQaf-XjE0uE-IEQI9B5n1MxEkVy9d3rFDgh51jrUL8JVqRvUnmN1yJ5x5rq6UZDDQ8NfaKRFQfYgbJNNxLcC3SQtv1HgDQt8uU2UnLjcW6GBJol3zwdAlAGchIzjFwUnVwrjO_rVFuOhXq5WuQyGtdHl7k0jIjfth-p6aVa7a5CKL0KAh2gdX2-Hww3CRaya2ECV6owcstv_3bLgLtKDELgt1yqjmxVWw6y-Zsyg_crTWkGzxHGfl92-n-e9nJTyR-F80NBQ1LQ40ia0AJ-Jj9lF2--GET012WeLsVOmUW5OYpQdhvNDMEnHW3wEUD3cVFeuWf2neFsiUDZLshRXhBXTF5ijqhO5HUIb4rjTlQ1ZhC3kSOL5t70_fBwaSslMmxEjnwQbtl93BOOGKIf-H4_ZW4z9Yet8QHyNnti96bKfOFVfF&prev=RQ2398D7B05A4137&p=3&pg=6) * ICsense * Aalst * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/9eb53286d1bd404e?ql=q&sig=d7e17e363f7ea4313ddfc4609f39742f0a30086c&e=dN3G8JQle9nMo14Jd_4pk9nIpqZ0fb03ngbb7wXo1hDCb4FvVB4JrWqg5tvOjmlwnMhRYALR3tCw7X-G2RAQwPHzSiuG-ITU3k7H-0_qOpTtRHaaPtk2Yk9p1hecU6XS4nZkfV3AT5puhGD6yTg5A_LZK43YNtAf0VMo7qVjmYMUWaOF3zQ0pEmOgq043i5qJBc-xg9kUrgQgevTL_Yaarsex_2mkCCPOcP4NVxgj04-jxs1yfPDlJz8z7GAZMK-P3pbOTHLeeuX_bVxOZpRfiGY1vmGoFXMhxaHJc8XRx0fiaMTDngBfm-zFV62PMf8BdGpoJH7we1ctkwUyYAErxsqKL-7QkK5n-i8AZhpNaTdbzS98IDcd1NEBgXnAieDxe3ze2hLxt1OwuqShvooPlJB7pktLwE_2cKvAwSOqwI7PcCi01J5DPr7SeTMYcjjx57cjop4siMqjpLjycA19Kfc_8cjCEQ6_ge6sOVIzd9Y2_z-2gsEpy6-YxfL-_LWG8XAGOH9sfoP98LX2LsZv55v5yVkXjHbom2fx0zLPYsYPCVuFjHi3MKPvYEYK0BTPV3gQdXzGLE4-vwjE-TQ_K_CbcCIyEz26etIIKF4CfpLN6K0KxA6dhL_Q3SBRzy0D8wn3cjiG9CMF6hqnOeYL2iPq_uKYu1efXZ-V8zP8muHMIWgX1PqG0y-6hAWD8Lp5A0wzUpxJGL1aSexXDEGF01y8T1OQObK1PLuS2w-ykSBuym_iN5anZmwY5NvP8aBo-xEY30LN6-i8U7Uhwhpp_BoI8G4nX4dOfaCJHkpW_ajMIkF7Cy_DlMqbB2toxpxSDz0QyLDz7Yzho5BmTpAmbklOq1LvaLvAGs1T1B6od0N2dtO7uc1w6wqUzAPSak_WnQlfvPJNR8KRwRaI42YfocT5Z9Da87Ucx6hvWnX1I8WwtsAf55l5FqkC8-LXNv44pXkDeK2v1xtbm_lOvhd74GPN-bRgBjv6pwhcAD9uF6Bly4y93ybhTSvGOP-J9v_b9mvZ8c-BuYEHroZ6OnavXmRXrX67mksK8YqviYzwV-2qSqI7KtULnZRuXJJNDxiXVcAxkz4keWclyiKHM4BV92JWCLAd4PF7fZfQvS7euGqxGCaQjcuDsE9IuyDh9bSk0eD14BEL9ne_XuYLCiUOWYyZ7jbYcc7EwSb0oQ1fjP6vZD9TI-r_jwRhOeFwr2qD8qFVUhwgtj5xB2_3FdCb8X5Ptk8-0T76eAnqOm8xtIdCRGKrRd-3eMncQDI5RrLjjn8fRKT2gBjnSnNNWJ1g_lbqHMXO2mnUXIrNPSM89m6z7Go16HhmQ8IXaDnDmTV-5YIcwj9Lqx2MqSxX79eoCSP0s-0UnmqYmzTmWSzBCEytqqeJ5IpmaWxAwvHIfUQAZ0PPYOLp1BQnFFnwWA72Q&prev=RQ2398D7B05A4137&p=4&pg=6) * ICsense * Namur * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/bc8910d20733968b?ql=q&sig=f6247b993dc0b351fa67a5d1fac7d2a5260c203e&e=JuahI_mfOrEbWNTctRiy-IvQp2bwXPhBXXpUFpCBV8s5Gc0bYZq-tb7VK6OXY6R38jUPCCG3iW_EUVnkRGE_XmUYho1Gz6Zd8U7ajCz_3zpIYvP3zvi2QurudPBCnGHyS4MZ3--ZmJNTv0rXEadsxvM_Ia0VvROU_Yip_NbVFIBzTo_Pj8wikxcTCTwEldleZCTUdBYxJylIXkxqoxec-zBDeA2gN2eYw34Li2HPP0Scq5-iu639s5ZlUSznNgHPJY1pJ-MztfMmrmCDt3L5LCHMa5Lr_sdfIY5PQUbhf10Lxw3W8UYEoTl5S4YOlrof3wRfsEnTXXMF8DliuWnSfJYh0i80TGTw4YsvXCw536rGo-Z4bjOM_qZiuJ4GuLHaJ96dSvM76yuhs0QCmqKjVTmWLDokBux9AETVDGOHt9_q-EMxjteFS1dhoz7R4BH0yUdRSi5g8HBCCPheUfq3l616riyX-x39TnfvbUTXsbwBhP4-G1M2pgp4nHPA_PtvqivKXQLHLaRmy5T3Ze6-HlSjI719MJAoBt5ozM_gGDLXiRBUhJGSjlUH3-iP9lt-runeWqhjbBR5g-nT9pIPwI-3nuvxw-U5jz114ItzgZiYgy6apoCQPlvY13uXtRYhNb4yMDGwZSLoiLvWaUWYNriW7tzGxOWcmVNoPsTNR1j-82SzDs3k-f_DSbJdUHZOy6UeqjuNyOq1R2ebNARGQunJANSJivIrpI-2o3T765RwUIPIO35GtE4nQ52nxUVXobiBnOdGf_fQlg9lEXP5Ux2c886otpWu32tNKO6a_pxnfZBzJOZr8taJFbZathApAhSZErfXZrNZXr8M60yok03Smrw8jL5yLaBQv6mOJ-6N0GGFtXPMpsealimUHhGfdd7uHEYa_JWqmBRqXbjwreChqhU26lOjvBD4kEOb_CDgLm8qx_5VFLTyXPj7jHCK7EA9tGszouxgz4rokk3EjRvm5_sJEID_dw5yG6TRkb2yJ9jRokurMOYLKu-IHA83dOB0DOWKLtALMYPiaZ1JmdGpgvJbvhWhRC1NBToI0ckE1Yzd2DproVrUnzFbm6StM5wDKutua98r2Oy1A9inMvg4tHE2q5o6QYWbGnngA9gVrU5pSlVeWQJcB5seQhl4jy3ENkptCSJwXoHkVL8qSqN_eBBuwNXWLOWT9rAwkFxI_izXz_hB_mV_uouShlqpQxxwphfcexlFVyhoJcQ7AkUzk8Jb8kYW5pW5ej5Sc79wjzwixef0UGrAwk5lhPSvN0-UihE11G8NNZZ1h-Qqi9MGpYKPMXzpvh4fcKIvJV6UB0BwnobL1a7zjN1Q1uw-VZtzFuFG7BOMC4oPTWphOiYODKXmKmDEiGr76StIr27Gynl8aTxbSECGJKdPhvJBTSzC72Z2ZBkrLiRcIlhK1hQ&prev=RQ2398D7B05A4137&p=5&pg=6) * ICsense * Veurne * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/01d1301630cb2d58?ql=q&sig=90625d72ebc9d34f33361cdc288e254fea7470ff&e=McEiR7YexM1-NS3LGg8QRcIRDi2eDSM5CvCMOisPFtNQlN4rVe9qdoTmKYMlA-v2hWaQyfE45bb6aCZnvOjGxPPzj9qYQ3Vpdk-1jU9OJTcpWxhDypWgIqLR0Bi9aoDAGbQAmWnJQ9RzThxaBgyiNAVzTWViI31mYCMo5I9l5FoGB0Rldv8pT6YS0-wCXkVnv3hq9tCg8LuZ_ZCGW9I6Y0m_V8zBQPCbGdqI4KW6wsMjR6fM0ZuPwrEAOJPyDsClb__9eIltS3l7wHkR-fGyzD3s-Pfd20RUGvxAnMErDlVNJ9NaDf7p3Wtk4zs6QFCjcwBKtsxR8_Zd8lOyN7oK75swVcV41BM__GTmhW38TpvUvlOOwVamFLqRf7ROB-RQKBmZgsJlf6sKynAsh-jKa2D4C3yqHsoiTMPDBx0Fyukyoeiu-mV5BAG-UbZNyxch6smeUwNir_lQ0EGlruZpsI2YOBGwyq7jDKNorv4R4M1q0v_-1yghNSgg3mcSHCiw5oLMhQS6hRQbaQaQ-L47SSkf6N5y59GsaP3q8O4cfHniQUjGtlcCVczBKp6gFhj2UwyMrgNB9cj1Nl4uCrKkFUtyZ_Zbh2-S9stFTpIuVYBBv-OY9IvexzwO0Rts6iAkqlvG5sQuid2zt7bd5pWbZu9efsk6tRY76Or9A85NSWxG12hMovD4OXKEIkVl_SqRxZ0V38aW8XQlwXTgygL8eqNFqQh6I7aYRUqiId4xA5bHID2lzf5Zpq_-ev1W3gLI3WCvonZUK60q6-kVtdBLdhY1AyrLmv5s9YfQxLODrbZLBJtVAWG8UOUX-pwwty02lq51FU8Po_4Vh845Bg3DnzPpa-ASCx3epbYd9ySppP4XhYvLEgQ3pL8-BYTeoPpTGo7dRWFLtgEaRnEN1KWoy6ILBZN0r5mObO3FgU5_V4AVI_yKbjInG8FXsD8-RK5MrpKvj4IGaRW0wpmbli6-qduoFaM5ICTzff1QRyegEr7c1TRVwqiYI3_97979Bz1wfz9eGDMEx7StPwOnDKnKjllzKt7M-od5Di7SoKJkikawo-YswCN7fyjYROiQsDZFspT0y5ibA9PIMI5AEFGp4yBRpPdw6fn2AjAhLbWRN6jscnmQMYqxVeeMQDn5sYp3zvbhiY5ID5hLuK1V-WHbBMdE4KG05b087GmTASIJ35wINvQ4-UAPK_XERZCky67voGkgthLKX3B2v-PHp7eFicjAQKT6zpo0kHaKdLil111e3eQFofNH0uu7qjWL4WM-NoyIFmhyfg-2-CkUNENi-NEnAZpFdppbeWD9gDi8r8CqFh-xxSjF8xH1eyTkuMtL3xJfWYOg_IbqpVRr4SjZnbpLdQCbci478mV3bcYgqZYyTdkSIUKkcVD7YoFyx32bvL35i1aC5D2SaHhzrWndo6hpf5E&prev=RQ2398D7B05A4137&p=6&pg=6) * ICsense * Charleroi * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Aeronautical *Design* Engineer](/clickout/c1b5f313f38ff733?ql=q&sig=3f80bd1cd9de10a7964be324977c340ed73d4ac1&e=Mr1FfP-u6fu4BRTPZ7sOQGQ7Dt5ck9mZA_yN_-V8p88YFQOyOSJoeM7M2RGpUFhG5sCfpzi7jm-uJlpsJ7-GaSxf8PvRG7etFHu6BDMmvdp47l1ulzfvzNy8AhRXIn0o7tGrIQ74ee5BEdB8s7KGHx4j1Mum0-Cnk9hbS-_vTPq3A6uDmO9fr2-UCJfoeDQckRqVBa3FZIJ1WrW-DWcvQAFy2eONuWbB6UaSgOQm1AcKDBTQlAKkIKkNEKt2fHrARtYcbzgO68UgsWDnwsWtZI1UDt2tTrVLHQc_K853pc2TCVTy5c0tmK3b3ObAFx5OPHuLZKQ_5drOJFRCvzP4XVz1Y6I1V8fP4ELpZ7EBNT_QZuFaZwfk-X-m8GAHzg53vBCxzylkqL5aK5f2lBwUJ6zWXfuxFlVgMSJkQQRepMYTFhP6tOc0cgDqsHhhR3_0bF6gUeHJzTXiHJbPPRhorSQc21xuueUBpREoNdgFslSJ2bC4YhUGUjqbn8AxADh0-VvNL_m8HMh8BNp6p4cltYl2eM7THsNZyfjKj6cRNdNPVI3ufhm5Rr-vXUf5CWxPV2Vh3hnfS-DIVXYhidIgkIzdF-La_MsgDWMNRP8UmNB9mxb3d_cvHCtbsmRVl1w1j--8Apx4ReFhoYgrvReBop7WgS0O-OrxwDpBhIuQtQZprr8-LDv-04wlPZgJanLfalwkjW8_XC6QUQdvENhZM_BZVhKkUcXdSiKGM0b2MKZsXIVKVp-o7Pmhkqb6RZvZgWqDSBPF8qRXK4x95GOU1LsOnCSdyiNy0Y_k-_BsZJuCHO5vn_MVNpEAqVcvWSjzZQxl4zKAkR987aTskbYt5LVAk9VqDl2esICImnIArh5rcRN10VyU-8Ojs2Glu099YXKY1hCahj4yCMvPancINTdHu0TJKHdDgFf7swEZSvjZDqnj8ijEniXuH3KrdbQJtpkbG4aJy3BuMaG3dEFqC6iOWJ8GHVJcxBTwVG0rdpeMk5P36EiuK5PZ-DZ41kHKPCdAJO0f1Tjp1c2IWSFcM6_JXUgQ7mkK3uvJZvwait8hjk_Wb_N21YcTzT0F-y29jhx56JwpphwXI2ryjkxPJgWt3bgCQ-zM8sh7dlq3Jf4pADguvzW_QfdQ_Pdl5spRA6gjsaNy44QEyE4Zkh5xg6IGznUBP6EmHHoDTIgMVmq9CVrdTub4JQlcTstnmpS5DZX5J0g0nRJsCPBoM5bqOChjJePNg_ksgLv-jDsA_VqQ6KG1rHYw8D09S6007Xuku118yUjZRQhPulXGUPmq5Eej3b1z_Fi4c56PCQcOVfK2Vydjag3DCGOJILZsq9sOP5XFRyfDnlsoNFIcMZ1tGxLm-oW0rrDdFpw--kSezhxwkUHHttblmqnBfVReLzhSW0FWudQ7iV5qYWVDoPRIcatkLUOV&prev=RQ2398D7B05A4137&p=7&pg=6) * AYES - Management & Technology Consulting * Sint-Niklaas * August 13 Aeronautical *Design* Engineer What is AYES? ... First experience done in Aeronautical Structure *design*. ... Prepare and complete *Design* Definition Dossiers, including FTA 3D annotations, and Part Lists. ... modify detailed 3D models in CATIA V5, based on available concept designs and established Aeronautical *design* report probem [### Aeronautical *Design* Engineer](/clickout/f406b5884bb088ac?ql=q&sig=51112abb42f075888dc1380ea8547a8a4cb13ea3&e=ZsUkbd9kKrci41mI13DUeCIKhLAPMdOCjXlR5Q_0bHz9DRUZZHaFyGXI1nNaFl4hmsG5P9Hb_BLmrmKVe_wbkkM7cvzisQh3mFXOyVBR6eOubJd99ZyqXFjv6uyveKFYL2MgjdEXxw-jCo2D-iIGXAAQUmF2Ue8cbYXDoDtOvqT2_BLRbyo3CiVErS-zBfaWn0ERlm48NPYDwl3kjdM9I0tRdLGNbp6hgavEvD5g2TBye3F5EHvOzo1ieSxEB7Pl84tukIMCXcNo6aKI36tqB5JYKd2eeAfRnqD8xpUgzQWgHIuZH0abMjRsqKfqbJoNfJK_D83J7L2iNu6mvn7wcUg6eK4_g5niXktWyiA53H2yy7W_AzzH3RRAPRIEsvW-wWrghz-O9Se6XHhDqKPXCSUyRxfvSBVNxitTCV7HqigitfzJ4q_py3gRWw9mhcTboDXPjTzzL7PIxG-NpZ4kIEh5fjFFyebsFxEVoiyw00iebJSdiEs9qUL-ZNd9npGKCy_aXcfHHSp9xKKORBN8vPzHlHldV35nSAEHNcdeC4BYxHH1TGZYQsG_16HpEpgikFLvSTSITz759MLqbXET4ECoqYL1Jm8jGmK8qpHAo0f7FXB1ckYHjHzYEOCn8RpflSEWsxJmX91tSOMzT9c7rYAg9BamEBaL1iguYJKgOXknVURDCv2AyvNuL2pugfHktgwPyNKFZnfP_UrqlfE-v4TZQ6FzniGoAdtXNWmb0NNETKaZmiqVvM-ImwQbtp-Cf6Zu3AxSm-ihHYoLtJLCNywrfrST1TwUpfVkhJFgbT7LUg23dxkc1cUZJgmHK5fPwGPU8y16rQWD-sxHTmr5LEIcOiXx_e7cMUhTRU_nRi-TeFF-yvmYlpHvHZlg9X25I_DbfPeV_c8Tol3H7ZdT-doAV0WEySQmAr02DvzGN-IXKs5qsbwY_YfiFd5NQ_c9dmumreGZr1Zmo3IpzEQcl9nZPsV66YSLFncFvdLi66rL13ZInbYEjNOcbMHxkS1-CMq4hG9p_IUjJQ9FAtWhY2sn65PO1226zDEHZ_lGGlVC5C_i-VW7VPHnEVwooUhczCeMl73HFI1s5LpDPXf5uthzdj6-jZFHDL7az3QJh6R8UfgRrzp8ioN-xVJv2eEw6rWirXesyAFT2KkvWvqXOy5jUfh1TLpZPNA2Kr0iFgHlMb6wTDe7V4f6lWgm1t66MFKpuKEepK11v3axMKLhM2ccdE2UVRki3IRWu6cXAxcADXjIpKqd325KEL-4drMga7nzd5Y-z3_ipy2viZwETs6O-QwOTKPM2Vaes_QbK2kFZg7cQSJy27_DRavwyi331Xng-xluF2ZnDiN35pKpu6oJ_x4UlIhIN7sg879UNAS6sw-KxZNKOD1bt4tgr54IPMf5qt1u2VRKLlk73NcCB3fJVWRklYFR_Q&prev=RQ2398D7B05A4137&p=8&pg=6) * AYES - Management & Technology Consulting * Hainaut Province * August 13 Aeronautical *Design* Engineer What is AYES? ... First experience done in Aeronautical Structure *design*. ... Prepare and complete *Design* Definition Dossiers, including FTA 3D annotations, and Part Lists. ... modify detailed 3D models in CATIA V5, based on available concept designs and established Aeronautical *design* report probem [### Senior Digital *Design* Engineer](/clickout/70989fca4eec1cc8?ql=q&sig=eb8bdaa45a6bc2f5f72c5a0de8d0f0dac43e1046&e=oOB_DrXrelxsQVqBYJ4b90uVvPJCJCsQKDkYgsgEc53FWNiieAYB8oIXqzpSf3IF1lTxiNiCw1Cb2mN7Hr4DSThU3Bz8xGt48T_sz2lB0ZtxNs1Q_HFqJF7vHX2VT9M_4EMfXlARIQRYgQwrXaOo3XqlLg-FvZWTPw9HFZ1znK_0fZ-M8W73mit6rssjZgC871HMnn-3711iodaiEauyWtsoaqD76sWMrJPovZwhimJFGQUNkL5QtfpDIMGvnn_3KM_nqIbL7_v2y0xUD6yOtLd5USP0exOpxpEyaazd5QjeCAaWPwoR2z-HHOjxik4GHCBiPouVQkd-XsoJimPdOY3ywB4nRYrGn-ULGKU7G4hTbwIEVC4v2cHS2WTeINpBBEyLZZWrBE03WwqUZaKLcwYvDfgR7esk1JHGABMr5Pv9QAea-wtV4TtfvDxrenOT3FhgI0Dm8R0CYamWt6I-QCWE_1oSQLDBGpzgev6QU40GSypYnrNaCP0t5Yo3EZ5xp6qE2TCXxJ9KiOXM_9fTLBe2rXew7T4p4NqOSS32MdVqy0z-SWeSRdY9Df9eQzV20no8OJ3uIraKoT0YBmHgcE2wwTsk8fVXoCqTExO75qBfC58pkz4MGG77RUr0bQNzTrNysHJAgPJonobxG_xlI4SyBGOP9vHhW4jK_kWVI9waoeHailXj2UH57U9mM70u7m1MofDe-xm5nahjjHPSkzilUcmP8InUXsnzRiPHnR26mnO5f0ZF-iV6lQnpptmDKLj2gWY1FyoVbGfMbHeadllz_YXSUXxST3bG8X1c5Ibb470vVrivnPw474q_uPG3lUQvxNBfHBcbFigkheyRXxKBzhRDbIv1r9I5VCGTOEdQVC-Bbz7Ctuweo45CypGlE_q2pph4tXNtr_1MqzJcOFh9Cv_9FcggPxhdDVOKJE2zsKfT8zM8iyPBId4ajrFDilAyxj4Ld-sfCBbKN8XRrq-F-_COCy9PQIC3XqrItSq_-4m2mGG9R-E8owYeDuk_vu3H9MPLo3DpiQWG2eTZh_qdwmH4IdpTD5q81fBjZ9GPmP2nPrjeA98S81pCR5Q2X7wQfl6ETPxq0FI4GLlUutoENkyIFEn5vSUK_6WSczQsfoIMTz1Sc3pDIf-Uyi0nVxIlRFtMuTC7y3SPr1X08nmBL6nY39UUomfeY9n5eSIWvDh3N4Zu3t4QGKYHsVocX90mUhzTABWhMsLDRN6wdF7V3Eb-MboHwzgqZEF_-Bb6GRfk7lIRTG8zZoSK2ijJhoyYtVMuqqcS2I9WToQ-emoFsvWgULRsRq4i4N4fqF_HlvVjsUVsnXY4-dpoe5FWxxRhm_Sa_tJsNc_DAbDEwqj4qLw_N0bhPusR3KUwMJhJpALtGqNYRzlpn8Nv4hkb73DB4Bz8BiDr1QT51cSHk_Ic&prev=RQ2398D7B05A4137&p=9&pg=6) * ICsense * Antwerp * August 4 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/cf1609bd0b44f077?ql=q&sig=2f5a8ba10f758a5481c7d15a967c933e30f257c3&e=zaoygW5ooNKKuZF-lOdvoHuNqai4Z7hYtI4mcEMbn0kufSZll7gV5pSk9UOfa_hppoAqo9jsT8Een2CGKoMr-zBqbobgmx-fkO5Xc1EdgJlhDvMGZUogZmpkKu373xdDcP4iZBvJFh8T-c6t5JDbPjn5YuJ2IwMyl2pjnanPZjcqmh7wpbG7ULcjWKiOhnvwgFI3NUqsFtAtlPPHcCm0Ni7qYP4Kdhk4gGZJ2CtRH5pytUs7WXUnFTJ7e9LFoH8rHDftHqkavCxo2o4fm7a4nIODGBz21CYC7_pT9Yj29VH8ayyCHenqJcZgWt19PfJ1IzqF8l7vzaYrKJgp1pa5LiYA_tfu6MtnSsiSy5fiCeMER2ApYS4uDC81vn3KwO6ixHBw11knoCiSa3n4d3kKkLUpY9Vq0VEjWRo9PTsTH9PFMomSUpdfHk7cUGYRAPDwU5TEb_SZSJsaJb_CGLhi-j-7NDJ2ETAmeQpfs8-f9rDTiNL1VYGfTPpSBNmg10gcifP5ZswzUPbNUUfqW_VxsWMtgvA2kt3bpTTF2bJsjziPFsjTLXGScliNUU9mLzyzhroyBVcQY_Ic-22GxImsdjJeBOjl0Cup23YcxYmApMczLpscHjcEU503-M5FK3DfmfSO9eJPXDrq97nOObOSrPxcOikUQlDptA4j6_WkJiTqyu7m3DEVJ8FqYrFEsXvpFmnxxNyNwt6RwhjubN4rMxYbjtL-oh2DgNNgz1Nz3kSkDiuGCICgrIB9gRJb_mZdIaYsP_sgFOsvr0Ger0U_kKzyu70cOGNTZuQaSt2thVe9jBdb-MxIFap7h2Wm1t-Ka-pjBiDPHrKGVuCf1KT7i0KvURn2MofL8pQudx01lCbdOLXv-lA0qSEr_7cBOKm4mTvQ8Sd_Sk-IkVZJPn8Tq6IXkAHNm6ZO53C_Ao7OuFa7XhTJxizqQg_CPZQ7cwZZwz92sKkZpeF83mUz52wL27rFR-T7nZBRY3R5XvRipyoC2nycKCZnNOQskSGxrfPLqITgSXrTs7IkqgMSPPFjvhyx6fb4A3QqUgNdA5e00aQG1ejYflMhMKFO33KgRogWzikQ1jqES9l-JbKvlCNND0IEhwITdJ9oWu9Pvhq-Ph0OGskMIJcSSjvUTWO3oxNF6zoe5Ltl3r_BUyT-w7GBBoYc1wotGIZ3MbXsm4PVqFY_L60i11p30EdjwXucd_hLOfex9AwcTk39FA0ER_TRcey8P0xfrRtomrFr0tt6rBPPuJnkysuwSyGUsK_DAhXkR22TNA1Gr_I7a2vc24mPYCH7b5IWhH-i8A3nOXnmVMOa8Zo0eAAEFGG8Qwvmp48w5lZVP5o2z6n3o-W2_9SWnN3TESQ6OBBVEWOA7ofPqbzumS4WkzUdZSBR7kp4ZCLcyGDcK34YP1fr-3Nm71lME51x&prev=RQ2398D7B05A4137&p=10&pg=6) * ICsense * Hasselt * August 4 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/d78a997b1dfece4e?ql=q&sig=ce8453bb43255dbcfb0152181921bde4340d96f7&e=H5LbcDG6cMC26GkqaxJwoNICagf6BUmezYLZyjmc9pqatj-lZIMGBxI1yLK4g2RVA83-8zzlpEaUu1HzBvNyr1HyyKQRBQPSwkJqbSDza6K3nYHa3lm-boh1x8P3WGxRnJqY16owJz6kmN14rAYn_990FgmDcgWa3s3gz4RG9_jJydrADMGF3E4usP0WrnhUAxsC6NZpLFh6A_nUXOr4DB8zok241e3wA_edN01YnhcXAc_kDuA5-7J-AnWOq4L1QJbYyfcLk00BlVUc95cudrJijHrjJ48mcY50YpGm3zSfIGTNpXEkRR7K_QXbAKtTEGMSjPlTrao1qjr7Vs8qZrZfbHOr3YKw9k3cU5FSXwxmdOeFz2M0JNA6Q0vDUnN9zIHwDfNEOwNotNFiAhu5vYztTNTQlsi20dOM-_L2LzSxwO7ED31KSRqX95DFKU-2JWDzCKHu_PCeB1mx9KVYRdrpUTaoeuZP-tmcilVHSL-1k3mYSJ7UiJqA14vK5F___-baU-xd4882CPsuAxqiqf8ry1FUNKV26wLcLRxxjq-sdtX8Yza4nR_5IiEXOyP5LB_m5bGTGlzDUw4UpgGZtsDqXqlbNZ0zEjbGIRWWjdgmbNls7Xjc-bUsqYCUa_671XxDUV7E2MsJVb4nFGQmUZf9vxVzyhcCLURc4tkU6MSIk5Cy9R9BUcFpS31WcpNbdgabcbKgZDtsJeCPJiO_H2hlf2f0ZsnDRsGqKN-2sSbCD68026ZAa8OcLUfFp0qWINR-YhhfUxlbP79RFXJjJEDCiO39tYXjh7PXN8UrqYEySv8VbqNapsY7PFtc4wvdvsjx8HKJZAQagUsPXLrHXLVZM3iAv-HFn1g9kD8ZkF-AoR0fXOPvAUIx-FFqVzPPtO_ETWz3MVzjB28uGU_a4e6CKPDLq3denli5xvhVLsCqO7yedBMCmbnBLQAkO6w_OvJqGtuBfjvSiqbtzHKooFTOwZC6n81cnRhF5Wh4eFgSDHYoy-NGg2ecPUnyceQZwY5W1giiZLqt1WipCUivLZ4tj0HSdVAb1W2Q7X8F_UMKKZpI_JqotXpBcD_ZquIwK7Dr6DlhLC1qzFlOi3lJweHwSMiBGUkYqyoE-uVGFB_4VyQ4VA-aeJmwihyBo0sCy0KfoDCzw92YCVk6b3w_1VO48ryoIPI6bP4n8dNWIbZ-T83jUqC62a91e-aCs-y9OIX6CuEk0WvPIujoRDPt97Lw8cFft89l5mbAR0YNvwnJRxzbilZaIsInZeamUdD9LnhEcxTqb_gilKhBWTx5Pn0eQ2o3ep8BEZGYJl__beZeuTmfSxAzNLt19AZxtvKrCyKuWjUBu42zFp2wTs1wKfYmbeGxv3Bh1HWrDdWHKU_xzytsGvASZiyWrAB61xNSWCMAsiKnzs1iXks87KYE_w&prev=RQ2398D7B05A4137&p=11&pg=6) * ICsense * Leuven * August 4 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/4315eb355981494c?ql=q&sig=a9270601ab15d23eec0a44b1b9629f4c06edc409&e=7gmkzQrjhD7zmL1xAaLDBfAkEfT8kGrA6AYSUP2EJZC-ON4GCtie2R3BCLMityCBTHxbEhH8ss-_b6Aq6VBwUKuFSmrcf37QitkouyqPP5YnHE5YTveK9qlQn-SLrO53g5_bnLP_WGWWiRG9Gwli5TcfA1EoTiSZNBbkBl10qdQwo0y3VKmVy8G1iNH-0ezy43rr2Q-ZHTVRcjqAAhjVsGMFaDVIoNKxlRBVqpJogeHyemIJE9hsybQH6twNbciRgl9B1u5xwdbsL3WB0A8PNp5oMM0XR2FjlNYMrQwXRkZ4mCjsSDH1qYlpGTMrqhsp_4u7m7ZZ8N99n3aP78eQEOlnDlD4pEN5liW6HLUJA70FxN5FAM7TbimE5sRZFRgc9hhbYbbsEj6q8NQpE0qtmUnVxlyc9p8UnMynN_ntcLEH9sRiWC_bYSI1MZRQ4OmcH6bMADnx7F9-eNkQRbiJVSDI_NDBH8aQIbOfvCmnaQgLjWwXhoCRqpBXcH3gMedLsIb7ufpiZdnyeMVyeSuXMmZ32EKNssvi6li6QYonnWHBfCh7o3H7oarMsFOFNM-9TPAvWu-0tIyVIp4NXhxxHrdWBEfWHoNURihGxvP0J_0jJMO1T9Eq9ZdsmY3QAoB2YHM3G_F33scCx4hTP9_OOpLnvtF4z0lhjWQXuspJSwe7yrwEWaW3vKeYX1fMqtBAEjPi7gpYarTbGy31h6t1MLQhNKaELgkYbQEenu998DVXQTgeUWwIOc8Rq62hMHx_hpo1EM1Uv1h84D9b3noWIE2ZJKVhAd3tiBNmxGJ7ltA3W55iweY9Ksdog-_tcTueysaQtiPUJ5Opp9V_hmc7UkiIApdFVK365ZxI_X4FeIu4PD2N316G1qx8rH1ZUWtaXmzMhuBg6a3atM-fwCPdCa56zOBEx-PDg3lL18kIXKdF9rUQ5rbwfmwOeXLvGA90ii1ByK6gq_4sJYTT6Z2pH9SVMoIM0d6XwX2__sRbaSqFaQo0iG4pZnWF8B7S7Fz3aLhX8W-nK8IUYtbV4lqgcus3LXYpMzaHJ-dxxPxYFzIfeE25U6draF4NfOPSYmUKXAT-_3pyj5WOQY1l-2L8hHMDp4ShpS-d8tqjug8K3kGc9TMiD0QcMJqCvZ4_ZF5oPeBIvhrjN1jM9IURUxQgcC50to_95IrHGwwXKFHqgzNqdpQ6_lA28FLMxFED961P6jwYwbFEd86izyNzNgZ2n6XdgUjXorWQAcaegXWw3fuWOKfT79xC6dZiInP-PqHXhE_NPOWDdZBXb7bkFLFSXTS-H7ipMoudN_EjXChs-Fp7M_MHN4HP6w64NH-QTXwlZtX9dGcYpKDvipzM4I1J0hIfsR-PCvAzLJOOG0UaHdESEzxw8kgMhSiAMn-ZpSWoeEaYRDzz3mN3OAkUamJor6M&prev=RQ2398D7B05A4137&p=12&pg=6) * ICsense * Bruges * August 4 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/1662e4226df63f4f?ql=q&sig=aa3e101d25e53e2097d09543c1469f6c8261d0b5&e=XMI6xXNRyNyz67WGmV3H0P5KH71b_VuUpd1jqQpC1uFz0o2MReTdKXmoSrRrJ-j4hy56fRvm6GRncCOnqCtpU65VNEqzJN9V7bpQFxTXJmKciQLfCncadj9AklsTs_p6xUTN9wARbWx8v2rlS-RWRTGPHy5yngy-gvf6k-gOv2zHXvfu_S7Fyzr5_QRjDLA0XQIEb5ixpVffoT5qOAOmhgseMIr3ZXjuMuSl24XGwYLspzmIlp0V_Ccu2gn0l3d8VgUO4ZjJZydrmDddn0wA-bcmxpVSWJ-FhN0_3MrdQom3IsEgxjCcr2eHJaqPntsVKJlFrD31av1PHEzqL_qOuRVEIdNDwsr6NzUqgKGDB5rp-QhJpu9Bap4phHb8ZeTRQki0Ufz1qNfZN_oqQdOycxAdxQ1SC0cy9wtr08qXdT-PCpryeXIFSS5TPPrEx1H3C3_BmfnvfV-JxBe4TwxF83CmI2zsUFq1eRBLiNsT9TYTOPgBP5IQRjXDd1BPeGyW_hXhJMoXP4QOISJ7P36YD1cBX9-wpxLmuKyUwroKMWfS2npSTt78qocqyC_9X8VV1knNVqljyGIq_13HRX9_5c02e47GYwRtEfVrcTpegLw582nHKk750kWk_78TWlMxRrv_uglwb_6nssKPMwb8dZdHgF-nEAk-UH31TueKdb2U0d_iSAzWdGW2EwEttTB-TcxbiqcglDTZ5_bV6WfZKZJRxlYzSy6p7CljMxvbRulq65-2mMo8t6p-yzp4O_gNJQDVXRM_mMaMe6yxrG9fO4jf33wzMjVG-qw6HOBKwTYgIG3WJb2vHbc29o334aBc8zAhn1lZaaO1czNbccG1xI312gt_TS1Xwc0X6QfKCRSSQkOG6KHaikh4XuadFcb-gGQzrM8MRyus3wvEvuaZ7RM3tm79TlyV40VJoPLeYOmlt_HhPYGlht1MMTHlCMdookuTuKxYwEHBxEj-rx20naoRgXGjbtofU4QThy6Hs1VAVgo15HgsNTywNZEu3jOvwg-zVBVOkLQD1sLH6sTlpXXGIdRqFEhHJ5w4fame1vjYQtjxkXj2SCbidMOv6FeJAHwHEdedaBQLiT_7BqXZQQfpBB_fSw_nsDtTqnUF_DeYBEmbLyPYCeE77GcZ716kJXmBrRDyr2PyN-PNxbYd1HWDQYOE5aA8fG5EEG3dfKHKCgNmPoyMFiHpBcAFTLMwME9cfWSGPeJNB1ewTEXF37x-INWue_nr1hVTo9kBLJ5wdJ-427fxorHzUMzfMN_uLcIONSOI6NXnGY9fcV4efj0Wm70H2GzYLVnYxqjQgLEUWaV0KXIrdMC5IuddpgXBpYcmm0ilKjdEr01wmzOlUEf6FAg0XSGOofC8bQskffl992toKJkL-s9RFivnRc4QjWRHo0N-sjZs2w53pyjCRA&prev=RQ2398D7B05A4137&p=13&pg=6) * ICsense * Ghent * August 4 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Mechanical *Design* Engineer](/clickout/82a3cf45f0534e68?ql=q&sig=e2b9de74ab7fa5dcd74d5efd8343a7f2a5fd547c&e=j759pVAJiGdKdKjsR7d65nTz1XJFcBgoU01jSyNQHAMNOkiJOx6SldcBfBLGoqmxOhg1cOFdI6f74enEfPAyp_88xeG3JE7YZrn_YFqvXx0zzvINqQCzRfK0f9dNGAb65dw5L0IMRRTJGoVycUsKNBioctOeuqHynphXbXuuGSYTdBbHJ_3BZZe8Rxle5M7uu3xjy1kJ3zUfEL8S9riDIXdLFd6sAlKpVPDn0Fz_2x3e-wAkbqerfDdPlPxlpvZJCmOVNUmSrKr1f2ipX5-6LjSecbUMjJxZauUgTE7y2qI3vIICq7scSiz7PsC-EmpddV8G09TCwmVoxb9OWQBj16FtjaWpyW9sBjtUUlJnpWqzO01plHSqmfizkKjQUFrOjaARhltRfJrboJNd2Eo6d0GFsGSKwy0B6X29iZV195zGx6gTRPWDai6z4YY9rp0KgtVnW2xE7L7luA5igttJT6lDHopjekol0ApKkTa9h63zvw_e2dZI1H83_7z1KZ_aD86gr_YXg7AR9XAl-ZdebrjJW_hWGW2PHSnEe4S9JYDtGotvAOJRmybnX9yOyE6hkF9_0i8Hgh98dmn5Ll45H79i27LI5g5uG68MQvSafhLdmxtvy-bt2ifgfRKGiPRWBj-7Z19kzRcBjyk-nWhrH0esOiuueOU6BUtxPv0rm1-qSJm2lEFq0zv2ESIQTiErG5lb2EAaLCNXa1Ro4-druFm-JGPXyULA2grHlJNprK7ydV02vJP7Pr4N9BisvOzXB0-zkgSX0VmeLKSg32_YnWLQao_-4OwzAdtsZwhVa1klfFhn7dHHblkH_I0wKXr3xt-CkYaaXfWy4EYyIQZYsie5iimbuGBHklP8uWIUcfJYgg4zlCeQTg-txvZnCEct8d6G34C9KMbZt3a24JDTfXzCuxEeLaKECghNs1-5pQAREcLrNJTEDHkDMXGhk40-vjatmlWkVVnYbUc8_ADjUeHHM49RbTrERNaQXEQdxoOMyiKtfwA2uBNFOsYRnck0DgdQ3KVziR_xTfitcLu7RuhLhjWC6Ue6K9ieMOl-3pyggsrlHrcxif3MyZ5lWhzDK88CGRAwZPYN9lSTfszfGmPAUMiV4uASlO2h2nJdoX28Mg_ICkzF22ybAQH1GhVnHz9NkJm05aAVql4MQXw3R9DKWksWXiLA9tWXCRRzII-0mjD3cK3EABy7WAo8BDUJYgqhCu4JO9KWMLIsSTs_mwKVqy5KZma6jQyXbL3cNUMT7WGRQtCOrhSt6DOXXy_FA35fEFAaPxg9NH1RbZvyel64BF7YoawxkOFwU-sFpW4z8o8jZuYtye3JCVI6KsVlBBvYCQXxrAUl9JQUlGDPvn9sKovPXMkh1vh6y9avD61eqTtb8K21FZO-4eRiWV70y87Z4ZJzQPb4MOJXfhAJ9UAD7syZcGTq98QMsbsBEw&prev=RQ2398D7B05A4137&p=14&pg=6) * SII Group Belgium * Walloon Brabant Province * August 15 We are seeking an experienced Mechanical *Design* Engineer to join our team at SII Group Belgium. ... Our mission is to contribute to the *design* and development of future products and services for customers ... to the dimensioning and validation of parts (strength, fatigue, thermal, vibration) Participating in *design* ... degree in Mechanical Engineering, Aerospace Engineering or equivalent Proven experience in mechanical *design* report probem [### Mechanical *Design* Engineer](/clickout/3b95085c4dbea2db?ql=q&sig=972efcc774c402b4ac23aa306547445a211a2261&e=W3EOPALyeY4TBzTz2YbEgLuCMkgsPN35Y_bAmiC0Xo74OHyoCtjDb_qicmph1ni2k9zGHm3kjDt18rdYCpS9Bs6qYn8NlTwz1KiDkM8kOasrQ9JRfy5JCRyPQdC7UcdsgiKPI3H_fCo0Pp3-z8X2o55OWSQPwcIxprT4hBEIkMEGBMwPYDFdHwUFfSSlsmdDCiWmVPGcHVSUR1b9motZA6T-cPAwDtEtj30is57hxLT_rX1FBCv1ETt7ioWvoGvF3_bEA3gxMnn4-jgnsjDLoTm20nRHtUUTOqqnOIEOI4mQL7YzHIk6O8K49p4erz9O71SxBbOlSZ4laFxXsRwkTJZTSpUmICYsi1OG9Gn9vn93axaVX8vOdfkYin6QaE2mC6lYgWPvUx6783zzRLfKPTBpKc6ichkwnHaPS3q2Uc7rA_Vm9DujZO39bNoHhUVl1EFYJ0ALoafHiKNL43lU2BV2qppfUKry6ly5-YLldsBmnWmvFZXdvA8mGJatX7Qx1zfZqgAWMZE-mK9QudcPAtdhc9BqAQ6wJ1vG6GZ-2THTbq37WrlLAqF0uzqZl2JrNDn82B6JYWqh4T8SJ9VI0_hXS-lnZUmFDuvhjafdU0j1ialF9QGSfXWnLCjjMWKBxRe-HXDDjBKJKZ1AuIs2dQLKyky00hYCTjfzhCY2x9mWqK1rg2QbJQKXabJgPtiJJunonAy-j6ZbK6iRWe9depHZ0gXfmbyxKEbQExVZDu3vbaMsVAthiolWnz4_AW8YmPWnN8NWyTfgTk6p01QoGXimwK8P4qFdtxgqibiD9GJOUKtiPaHd_qudZWJfUUYsGLLtPOtPpD1iFyZ0Kiv61NmKB0KVdHCQwH2eyF-GWELsRw_wPz9IKShTSpk4BBwiY7bnuLcSarg015A6atLN0-lq3TQhHL77DMdGZSMQF5Si7vlYIDMHr4O_WkNuxVBf_UqiyFD0ZYu1fbbAbkybzZz8kMB6VIW2oiKP7dpB7EewLuySiHKOxKJRE4iWk-ccXZA0WC5Tum1jZvUznl8hA3Y9DVwGDVqpoFmoSWWNKV3rkVdU77IL7DK3cYzsFU5MlnWZ6MpL4wROtnxDO41VHQL4SJZywmRRLk0xPrXTM-z7mxX4WHJI2hV7hyVSZhXPxAa15CCXxDn2TQbDbFJyFpRz7W78iSF3-ra9FhU_X8FLpZI6dMUA0OGr_xA8lGeMG_UQI5TNMxKjvsCpmKyzR7h5wZgDaByXvBS42olRlgnJn0QfqVzpxXchvjj8fFJZMNk5wp8a5o4bqHMUJS9RRdxV6v6cGl6ennKAo_kWqLiyhehgXT5fKhBCe8TsDjZFFH54j7BFmfFbNaWdS0VrJQip9TkFDqP8PbfdN-4clamgSIH81o7ZtIQtxXNLHSpA4L9VfZ2HTv6oFxWR-6pq-PDLl9npD20JsjRUs2SkEB7u&prev=RQ2398D7B05A4137&p=15&pg=6) * SII Group Belgium * Arrondissement of Nivelles * August 15 We are seeking an experienced Mechanical *Design* Engineer to join our team at SII Group Belgium. ... Our mission is to contribute to the *design* and development of future products and services for customers ... to the dimensioning and validation of parts (strength, fatigue, thermal, vibration) Participating in *design* ... degree in Mechanical Engineering, Aerospace Engineering or equivalent Proven experience in mechanical *design* report probem [### Senior Digital *Design* Engineer](/clickout/e1e646388d969160?ql=q&sig=92ae6311ca9b5e2d2bb2d3283ed0c535ac166256&e=JLvz7Hmm6_sE-xY1qsLmkcPjQeNh86D8eIFpqm1SXfezE7HuJVn7DmTYmWc9mhdt8VvCc71F_M9oVyRw7T_rjq8i1bSUYtqKPtHwUMsweTlBfSiMSebH2J7lcVvy8xj6n0ic0frwB1Y6D299xSEBZBtzvvCOjBlNErWSvyQjZ6uejOUKV72DLrH8aAqhnqElvu1XA2jcAqLh6hKm0XzBpMd7aNHBAeJ9TdBs6hQNQR0-4uV5ZH5JWlKz_anKNvhEJOkwbfv5ipsouS2D9SloAHLlo5B7Nz8_FdHfDYQ-AvWH93jIL4AfUWDbmIwcykNSGBp2Q2TnRvS7IcPiOCZOreGf6go8u-6U0qf3FjK4nXGVriY0Jjpb2HQ3G2C7XkfjvUJz3w4nmCRepmXerURgNxpmPkB6EGE64X43hODskfDIr3QMp14pNUWlZBU-8ym2TPYYEndmglGbDEn8n4CmH-CNQsoE5XIueicLrYeTF3hKd5HV2XSKDDLAnfSqYdV85AEV_h8-7XfkJwd0ebDAY4UYcbmpCzKcdXcaGtWgNCselH859LgWmsTEvtvysChzthJXURwykFtX-xx7TQUuVnJfJ8saGugWPC36MLSd6JiTxxZrXwB-9LaBZSUUJ9bgB0kVYgkbbDd72_Hq95dWH7jXDyFqk4s5QK_2PBrYuyZMyewpkVyYmU15ytoK3KgzqCq4hI-M9EIleJfG2ws4Mazoq0YhYp9w36TDFZkWD9RxcO-3LxVZKjLOAAM4PUXmrqNF-Dq_05g7RH_B1SNqVlD6AdhvFlYRKq6gLAK4QVkU1-1iNPQHu6SkFXiO70HoT9nfGtKuEzJuHU5i6FokB3GLKH_qnA71Xf1SbZdB7A4ku52tLzwjqwYcsXWtL0zAraTh7ie98tbM53qxhzx4CQjoW7UaIEtPKPfGmThh40dE0yizlOL6kqyM9x5V2mzfyqxrt7bAWLqxlMuOpwlU5PgvA16gPkNcCenlvhsyA6IgZOXvOJ2a15nf4YRybtQbEhuO7NDeWv34oc3cRKoSDU7M0LzPGVppcoIgdLpt2x6G7_a9fzT64kO-2u4FC1qHeY7qQtqN5MvrcUxM57gLhB1BOwCraMaCAkX1iZO76-xeQzdqehh6_T3TiH_zgMyrXW0DujivEeAtLT7YxkBxyz89nslk6CX251vsnsyUnvhy5FXzZfJR5tSY1hXhF6PVl2fIZTsAF8Pt4uwCIQ9DddBWFSG9i-XVmrEqz_FO1KxVKBiqnGFdrGIDInPMQlnLGssQKS4-vbZO4uNPJGypSdex2TCTnlK-jhFMtReNJzAoauu0ll-fXcMEjz_xLUU3jdtQC7jGYDrDRMrn31Fb0wZbjNesUUgESUhlgnP84ulfLst2Vqjf_8QhKJxXCdTSurjebzmD_NWIQuE-LZUKKiQsea-sAzxFmcuH&prev=RQ2398D7B05A4137&p=16&pg=6) * ICsense * Hainaut Province * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Senior Digital *Design* Engineer](/clickout/a42585594cb0adf0?ql=q&sig=4a0cfb991f678cf8a205482aa97fa73596bd7058&e=YSq1wlTc2yGebz_dbtGtF3asI06fLuSeXnyiLNEseHuUNrDxmih3bxRQWPf1qLsrVcBrnClKhZ92i-1LoId_tC-A4Wra5e1FUXSKOkHwQF3wqcSM0cXRQAOwVItthZNLRZkgK9vczkShGT8bG9h18QgpS5GH4azdo61wHBBmh9NcsTkh0iZi8R0hfOpoo_wYPQOFDH24JDHuLYyWWQuUpxkJqMK10257QTysFQ680CP9WWjwLEVNbuPVxLM9MTRI4ymAxjz6oP7BguOwvIi52HJmUXjS-FnE-Ll1uOmpTZTND3fREH9IyPZP5-8BC2APGfoRG7_3xTuu-Kti1B0LzkOPwwu5y6qeWgcn1tb8H2NSJ2X2r78rD_PlyJ4bwue5hRE0tncCAhdlpAr6ZMfaCZtYfW2Kv_pxodgWs5XBHsrttoA2cm-wD_szmchj5OZaPqhw3X4SV95-tTY_LinLxaIn1moaqVaLU5v2K_ae1QEv8RQLXPbufozfJGCBJwx14_qZZcTM6dy7NY0j-ESmwd-jmFRGltREYn-qjqKpXLDpEE6jx4VOt0mB0ISVdPirabQSvWUBxnFZ0NCKfjN3C-BHQFHvRYpZiPoCxsQ-Ndf-y7loprdlt2zmRl_P1MW8_kkC1a1YN5DlrWBIA0ev7dNtoLl_sE6SPnHPtEV1Pi-8VTl8tQZbgy53OItBXIiVFVvyYhedZl-Ho4Ppcu2uVGt1EtrUR7DvVoasqxAc4FgG50Bbr1wwjF-cT4veWJzNeYAaWO-bRs_wXIJBCAEKeYDTVirx8sq70gdBZIPspOIjkwlUfhIiWAH-1heSLfGVFvZ8JsIb3e3B36Ps-UyzzC2iGAeSOmQmhLVOS7n8UtbAAb6Q7gOOUrRg0_CI43UiRemPYm0VPdVHzoRrNevOFpo4Rg0tDj8XAt4h16A8aNglRV82KvZgWgfi-iWXSRptIZZYyyzBXXeUyi9wWjgU2bwH3JhdZMJOQC5j69K3XbmnapomRvFUBNixOktd-MT4FbqclW8rvN3w2rd5nAHopKCAmiJSu3mhgmQ2irX5VHreWkiixlHw-O_IbRdAhFUMoyjafUuwPOTLFZmwO8MCkiRlQlbehll0YD4UvdCmgLGC30SHiftz5Qp4DS6Ft6VDhGgGjtt3IiZ0c3oXeiaArV5l9dpRN3whvsIqDrB06JtJq2iVCPOaZDlAjkl64Hg39DmLa59AZEZX8XoLyIjJMIMHrrKg2AW-6XC1uslSzP3V9_4Kzt-bedkyxGR7G9o_SbJIpj_eWFqq5W-7GyVX0B0q-qbquUCaRnVkFl1rGQD4NJD2tPZC-SWaiEvTgtGZZv89N28zTye5-5699mgcVjIlJI9ED-aHdl11WcjOIPBMas2-cA7QUD6G4Ib0NV7wcsraf1jE-XHTtOaqlJR2st8jH3QYdJA&prev=RQ2398D7B05A4137&p=17&pg=6) * ICsense * Sint-Niklaas * August 15 Scope The Senior Digital *Design* Engineer is responsible for the study, *design* and verification of high ... Responsibilities Study, specification, *design* and verification of high-quality digital and mixed-signal ... You have experience with front-end ASIC or FPGA *design* in VHDL and/or Verilog and/or SystemVerilog You ... You are a dynamic and highly motivated engineer with at least four years of experience in digital IC *design* ... of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM *design* report probem [### Aeronautical *Design* Engineer](/clickout/b0c0b40e7eed4224?ql=q&sig=6ebd40a559ccec5053d17ff61643fc30b8ea50a5&e=X6s-OvjSVYZAirnRbMoAS1Huubk1CGlaCMy1pLhdMLiFhykt91iNe5i3q7xDOlfAST_pnNvEOZEOcG1Fs6BAN4qQmDK6F4JhDasfKs1T4N2L4_pmmXarcraZQN4-utZIJeOOSKKgy3fZtMIva5qkDhP9mh4uKiZHLqiq0OiFK9OghA5_qBK48DzROymDbUX-Ky7H1pJCL2zB-xYn5hTbJpqfYuj2jGYHPun1Vxwm7NvO7H90SlbhdzGC0T_syv0u3BqSVfYvciHj-zlyuXVqlD_iMsskvyBHFVuCbjfpIrw8J27YRDvJIO4tHw3rjIfU4DSPNKtW-HVQpT3MCyEB2F-AM_zNO4vIfwMiqzs0BRTo8xO5uKFUf8-5QopKqQvqwv3k8VpE7UyRFdUwn2Bswy64JHYP8Gz-yKkFNTaju2IrWzS2K2QIIGxfDSDonVlIMDS2BEPPh2LBF7jEtJn1VJyuRt-KDSpYMDvSQG3F8oWX1RKPQVnzl88O7F6TBnkyO3WV7Dj6RgeMSLujy_5JtbFJH0sqoYNAzCCs9t1VFe0Q2QFe-nfShcCcJwhUQHvEh_rOKyP2Kj8Nb9oMsKyOWyAsUvCHY2XTDta5nzsbBiNFnQ3BjjPxs7vUC42VaT5JtX6DXInAX_lsIiPrpqQYb-VoL_0L3ZDsUV2JVWwonj6CNRFROB6cSNDmPck2k2VGCq7TlGZ7Jf9WKoMOhDt6R8bHz5xhiP2Ei55MoQBfiIXnTVl92wxCbHHNs8ybkqDjbvYkq6d4mbiP4W15MiQUrXhWKvRUyWEyiQyi9TVZBPGfStVDmot945a8GEvwDiihmEDiDZVm18kDRDtpyla3yIrTI1GDpbT1Dy4pgsXJ9FQ9Pi1wLAY1LBLLZNZXhhr1XQFf8l4-nH122TgzYE90bmKHexNseqrBEJiNI_GS0X20C6FH_KFrzCRSlz2WtTJwBx8cN1N4798xvltL3wbkciBPgX85tG-UljNejBMBGvyCYUNAoO_PKhqjV4rEcrS1nkZaUIYjCSEQGP-9Gjob7kQa19y2OgI_q7ov0w6zwE_kTB1KhA1NEDlpbhjzLkIpW08iZsJnhT8Y8f9jqAU5Vc6yIw6BXG5df7mSgBUftAYHLlzJcCCP0SlljTyUKW9P1NS31IuMq7lzR1GZ67EOQ9ahVYRchSa7JnO-ahDehe3IcwaHEKyCkdUoTtS7Mxu6vJZWYahclI-m_a4WzGViKhCldqo-XThwxm72Zu6C5gzZdE6JP6zNMCbqK3OhkT4ilzXNudM3EJQB05vA5EExnrNATAZZctl14LuTJ0AUrgp4AjlTvr_JBrzXRRPCAeWj_IyZO1iyCTlwzyJ-wkH0PxbxInv4mfEii1RNLiwvyV-fyIsWJTOIxBzSIWVF_CQVGzsElJfau7_mqp_DOXUG9aNpByVYoxnIUlTka0Rko4u-&prev=RQ2398D7B05A4137&p=18&pg=6) * AYES - Management & Technology Consulting * Walloon Brabant Province * August 13 Aeronautical *Design* Engineer What is AYES? ... First experience done in Aeronautical Structure *design*. ... Prepare and complete *Design* Definition Dossiers, including FTA 3D annotations, and Part Lists. ... modify detailed 3D models in CATIA V5, based on available concept designs and established Aeronautical *design* report probem [### Aeronautical *Design* Engineer](/clickout/2e81399084793147?ql=q&sig=47a7c8ecfcc52a5f6586b0da3527d7ff0d3c9399&e=Q0mFzpA56HEndv-_OLN7rPC3EujzmUOOgTGQqF7HfIDp3yEQwm-ru4jkWlZv2mOhFPGJW23Rp6F6FnqGuqKY3G0Jaz4mIgrvP1_cOtTfO-LZWnDiN2r6o9gZCQCwX_DDEqBu9dvlsnMawRCqUfsOMrUO7rueOaACWGg9kZaCOYuIWWYmyYWGy0kFobMQHn0MsuD1GNSbkKawQajuYAa7-AkouN8hsGw4pr0iVquwrLtEVSfSucBGEOOkRQJmbhM1Xzpl_Y4AmC0q0-F6FXv2wYf4HRQmllYMeUYViB_0gl9QjH5x8Db0-UU_2217cvWVBzriifAV-VXq_vii8ouFHs_DEwAtD7WbzCKq63DXOG7SOhalCbIG9DdijgRUDi2muyZmiG_w2sCxREYKo16hEF8zCmVrpK6VN_wvnKwOKByGQwhxkA3YJo_l7_JKAKZVhw_wrHDj3IVkHwhh9rRpUUxjDM9WpxMmCkbFgIDhTuJxEhe-RSnk1abXjqCk-WjwgXXZA5ZZbi99C4XWpw0b15Q_T0JdRRTY0OTkN2xIitw9w6bmtNKtX1xkuZQG4hK-1pUPJ5cybIAP_rvA5p0aX5eoYn955WGOEZ96geeljbGHwzY68hZLqkeh1KFKUyaK7gINe_VlXPSelWOjhMPSp2nzpsR7JN_Na2rp_cPmLeI2PDlghcoZmgsDHeuL3RP4_jhvHMK99EIClrk590MgEJo5K-zsg0XJVNSjir5wA-7cXt36pP4VhEQ9Ee4EduhsqpusgPfP_PyJbhrJy-zplRL6e6GsixFHpZNEm9sSFdyW_yN7nxVnfGXD7ZmwqdbmbNFEWCFXAncJwZXj5wD1V8IYPwtnUJTj99Os5MmH_ds9HL5b8UnqP6wjzs8C1LNbDunjd-xAR3YHqc4nRFFYNAfIskC8Wg-w5W-k7_8mDeHY_-JAylLIldWn0uLJuTJIsrvS8KnYlDoZwm9n1NRpysnioXd1sG17C5pmIQ8qjuSF2cs-mSZTe6hc-HHZANjyCGh8211AK5fdTM4wkOfZzT8MKYlncqqUlh2ES4LtBFvr4q-goul8Mxq9-NxpSmmCmjnORrfgv_smENF42IoeSOynPpzGRe7EfUfhjGodgc1Jac3tMU8EwAnNnAFNJ8tGHDTGIs0UJhZvbYM09dSGjUoP0qXtWSFi6cPWVww03yUF2OU1x2mtLwEAv8Cuh8FQy9Ya9oomtIrh4Jg7G5EVIDpejNqOiRhTh5DK6WYpNbJba2NT1M9JB8xPGhYoGzAxcGdGFYQ735uxWf_jLofR0r6iEs2QaW2w4zEfXKeyy_HNk0-5z5i__xFoAestQcVsGRQtwmrQNneuSUMgdFetN5pexLUQKNLiyuy-IsT1okr7H5CGYT2IIyFIat9hPdrvBhUzIKeD6jPMKuFKPqcmPhMCynJF_va3wfcs4reZT6uNyow&prev=RQ2398D7B05A4137&p=19&pg=6) * AYES - Management & Technology Consulting * Arrondissement of Nivelles * August 13 Aeronautical *Design* Engineer What is AYES? ... First experience done in Aeronautical Structure *design*. ... Prepare and complete *Design* Definition Dossiers, including FTA 3D annotations, and Part Lists. ... modify detailed 3D models in CATIA V5, based on available concept designs and established Aeronautical *design* report probem [### Mechanical *Design* Engineer](/clickout/a6e5c6ffb2cd988b?ql=q&sig=357c85d1b71f5371ba304d411ea0a1fd0bacedbb&e=ZHTV49C0pei1DcVkQMFIqk1lWfO_mP3kQKpI0toh9yrX_SSfZowyFJj1FoX1gDcFc99u3HTkJbaB_K5aQ6OAq32fCvYnimoQjCGbPleKldhpBsSVF0ujJ5Zg-X8UOB7C2Yz_2xpJCFzS6gqOFv0bh6KxRK3kV_nu_DreZ-pFgnS9zWi2VHoDwyxe09HJDvfiUgax0szsbtdW9K3ugiNW-t93_o5uBvvS37F3B2sgJdkLqgxm2JnyNgA0QRU1FEprsQXqMe63Rc1t8nCXV4Q8fAxRLuwoaB1cYlliuxZ8YOqe8xwzH52IiHlRghEQK5PTDqApe8K2qUBGfAb2WLrUufeOiVM-Ish2RjM1Pk02mMHMdUYo3Upk6nWydbEJBx8hm5gaOnDFofa36hJkR1bsEziF_ZoOLSOJ6IFPp12C2KyYgA-2ygQno5B_yF-4j9KPr0AOSrleHE_X-49W_uBaDd0Vk6vm8Rf8_RuH9f6CONYs-h9GLHhjO9F_nfbqe9iNQVuympNLtk21j8xo-jcfD2yB36x4Dm3ZLi2JDkqpEVArWrUW4kX1GoE-cxpAWAaSGU0_Wf2dJ0jftTxbjbqb7jDM908IGihJqm-F2Gv_S3-kHaDmwJ03CJWDPUHcXZUUD9JhzzlRVbax9m5YNrzuEpZtbKmyLfTliY-VbN0WwmDAQyYcfowQbCxByhV6SWzLMtKwDLpEkJB39_tkck7QgCtidJNcbwnWUq_NwVvwz_NmbppjWI9fXyisKnQHhotUEO3cBX7aG_1ppfDRUeNXCWLftnySEstDK3S0xTTdO0-yeZccgkN4OUOavdk1nlFVhLCnf0UHGRkw21pqSQEdwRrNBaNzl_761hNnUr78faDSsdSXQVCQehi_YOpmkKjrSbdbWtez4HPj4JtDKyZqj4SIaqIXLdY5CHiswV_7yiLuGW8oQMUu91abY41k9WJrrc0GkZyfUZOmD0M1XBZzjA8PpkfkbTtzoJxjlw-MjtOIMBlUHTsaQ8nceRyd3WX83HUCBVjrnrXY35XJ7JWQ7JIA2k5KtxA3HUsAWagsCf1eFJiOh0Z9PQOYE7fafcvnP0m0lvAwKIOiLzIkGeCmrv-JA_MGFJCaiK7jHHvey1z0bH_us5F_2eJBlpB7z3kXKrbdMjNv4p1nVJcyRaQCYDD1xEe_RlQb2kBH5_2MP8GRLf3cko1oiZxdPR05J6lxqgrHnLreyP_fItx33Ps3t_7JSNoRl-hzRIXMlMGUop6QKwLuH-xclrExanC6wYpfgFB-tbxJnlfsGE8HSOfXk2d8LalMs1P1x9uGunmHLGwxdyQB01vrn7EO3n2DpfJ20kyzI6KMs_NpJlGJBzyazX9sfSkKcARj9cDwEII2HjNAQ9sYci6CCUOQKNvpx8SXi5DJnp7ceUsbFuTKl9d3mPM&prev=RQ2398D7B05A4137&p=20&pg=6) * SII Group Belgium * Liège * August 4 We are seeking an experienced Mechanical *Design* Engineer to join our team at SII Group Belgium. ... Our mission is to contribute to the *design* and development of future products and services for customers ... to the dimensioning and validation of parts (strength, fatigue, thermal, vibration) Participating in *design* ... degree in Mechanical Engineering, Aerospace Engineering or equivalent Proven experience in mechanical *design* report probem Email me future jobs like these → Email me future jobs like these: OK * [«](/jobs/design?page=5) * [3](/jobs/design?page=3) * [4](/jobs/design?page=4) * [5](/jobs/design?page=5) * 6 * [7](/jobs/design?page=7) * [8](/jobs/design?page=8) * [9](/jobs/design?page=9) * [»](/jobs/design?page=7) [next page](/jobs/design?page=7) * [«](/jobs/design?page=5) * [3](/jobs/design?page=3) * [4](/jobs/design?page=4) * [5](/jobs/design?page=5) * 6 * [7](/jobs/design?page=7) * [8](/jobs/design?page=8) * [9](/jobs/design?page=9) * [»](/jobs/design?page=7) #### design in Cities... * 517 ![Brussels](/public/img/coa/be.brussels.png "Coat of arms of Brussels") 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![Liège](/public/img/coa/be.liege.png "Coat of arms of Liège") [Liège](/in/liege/design "English jobs in Liège") * 58 ![Hasselt](/public/img/coa/be.hasselt.png "Coat of arms of Hasselt") [Hasselt](/in/hasselt/design "English jobs in Hasselt") * 54 ![Ypres](/public/img/coa/be.ieper.png "Coat of arms of Ypres") [Ypres](/in/ieper/design "English jobs in Ypres") * 54 ![Roeselare](/public/img/coa/be.roeselare.png "Coat of arms of Roeselare") [Roeselare](/in/roeselare/design "English jobs in Roeselare") * 53 ![Bruges](/public/img/coa/be.brugge.png "Coat of arms of Bruges") [Bruges](/in/brugge/design "English jobs in Bruges") * 49 ![Soignies](/public/img/coa/be.soignies.png "Coat of arms of Soignies") [Soignies](/in/soignies/design "English jobs in Soignies") * 48 ![Aalst](/public/img/coa/be.aalst.png "Coat of arms of Aalst") [Aalst](/in/aalst/design "English jobs in Aalst") * 47 ![Namur](/public/img/coa/be.namur.png "Coat of arms of Namur") [Namur](/in/namur/design "English jobs in Namur") * 45 ![Ostend](/public/img/coa/be.oostende.png "Coat of arms of Ostend") [Ostend](/in/oostende/design "English jobs in Ostend") * 44 ![Arlon](/public/img/coa/be.arlon.png "Coat of arms of Arlon") [Arlon](/in/arlon/design "English jobs in Arlon") * 44 ![Genappe](/public/img/coa/be.genappe.png "Coat of arms of Genappe") [Genappe](/in/genappe/design "English jobs in Genappe") * 43 ![Nivelles](/public/img/coa/be.nivelles.png "Coat of arms of Nivelles") [Nivelles](/in/nivelles/design "English jobs in Nivelles") * 40 ![Oudenaarde](/public/img/coa/be.oudenaarde.png "Coat of arms of Oudenaarde") [Oudenaarde](/in/oudenaarde/design "English jobs in Oudenaarde") * 40 ![Sint-Niklaas](/public/img/coa/be.sint-niklaas.png "Coat of arms of Sint-Niklaas") [Sint-Niklaas](/in/sint-niklaas/design "English jobs in Sint-Niklaas") * 40 ![Tournai](/public/img/coa/be.tournai.png "Coat of arms of Tournai") [Tournai](/in/tournai/design "English jobs in Tournai") * 40 ![Veurne](/public/img/coa/be.veurne.png "Coat of arms of Veurne") [Veurne](/in/veurne/design "English jobs in Veurne") * 17 ![Wavre](/public/img/coa/be.wavre.png "Coat of arms of Wavre") [Wavre](/in/wavre/design "English jobs in Wavre") * 16 ![Deinze](/public/img/coa/be.deinze.png "Coat of arms of Deinze") [Deinze](/in/deinze/design "English jobs in Deinze") * 16 ![Ottignies-Louvain-la-Neuve](/public/img/coa/be.ottignies-louvain-la-neuve.png "Coat of arms of Ottignies-Louvain-la-Neuve") [Ottignies-Louvain-la-Neuve](/in/ottignies-louvain-la-neuve/design "English jobs in Ottignies-Louvain-la-Neuve") * 16 ![Waregem](/public/img/coa/be.waregem.png "Coat of arms of Waregem") [Waregem](/in/waregem/design "English jobs in Waregem") * 13 ![Harelbeke](/public/img/coa/be.harelbeke.png "Coat of arms of Harelbeke") [Harelbeke](/in/harelbeke/design "English jobs in Harelbeke") * 12 ![Tielt](/public/img/coa/be.tielt.png "Coat of arms of Tielt") [Tielt](/in/tielt/design "English jobs in Tielt") * 12 ![Torhout](/public/img/coa/be.torhout.png "Coat of arms of Torhout") [Torhout](/in/torhout/design "English jobs in Torhout") * 11 ![Sint-Truiden](/public/img/coa/be.sint-truiden.png "Coat of arms of Sint-Truiden") [Sint-Truiden](/in/sint-truiden/design "English jobs in Sint-Truiden") * 10 ![Geel](/public/img/coa/be.geel.png "Coat of arms of Geel") [Geel](/in/geel/design "English jobs in Geel") * 10 ![Turnhout](/public/img/coa/be.turnhout.png "Coat of arms of Turnhout") [Turnhout](/in/turnhout/design "English jobs in Turnhout") * 9 ![Hoogstraten](/public/img/coa/be.hoogstraten.png "Coat of arms of Hoogstraten") [Hoogstraten](/in/hoogstraten/design "English jobs in Hoogstraten") * 7 ![Izegem](/public/img/coa/be.izegem.png "Coat of arms of Izegem") [Izegem](/in/izegem/design "English jobs in Izegem") * 6 ![Genk](/public/img/coa/be.genk.png "Coat of arms of Genk") [Genk](/in/genk/design "English jobs in Genk") * 5 ![Lokeren](/public/img/coa/be.lokeren.png "Coat of arms of Lokeren") [Lokeren](/in/lokeren/design "English jobs in Lokeren") * 5 ![Tubize](/public/img/coa/be.tubize.png "Coat of arms of Tubize") [Tubize](/in/tubize/design "English jobs in Tubize") * 3 ![Herentals](/public/img/coa/be.herentals.png "Coat of arms of Herentals") [Herentals](/in/herentals/design "English jobs in Herentals") * 2 ![Aarschot](/public/img/coa/be.aarschot.png "Coat of arms of Aarschot") [Aarschot](/in/aarschot/design "English jobs in Aarschot") * 2 ![Dendermonde](/public/img/coa/be.dendermonde.png "Coat of arms of Dendermonde") [Dendermonde](/in/dendermonde/design "English jobs in Dendermonde") * 2 ![Heusden-Zolder](/public/img/coa/be.heusden-zolder.png "Coat of arms of Heusden-Zolder") [Heusden-Zolder](/in/heusden-zolder/design "English jobs in Heusden-Zolder") * 2 ![Leuze-en-Hainaut](/public/img/coa/be.leuze-en-hainaut.png "Coat of arms of Leuze-en-Hainaut") [Leuze-en-Hainaut](/in/leuze-en-hainaut/design "English jobs in Leuze-en-Hainaut") * 2 ![Tessenderlo](/public/img/coa/be.tessenderlo.png "Coat of arms of Tessenderlo") [Tessenderlo](/in/tessenderlo/design "English jobs in Tessenderlo") * 1 ![Châtelet](/public/img/coa/be.chatelet.png "Coat of arms of Châtelet") [Châtelet](/in/chatelet/design "English jobs in Châtelet") * 1 ![Diest](/public/img/coa/be.diest.png "Coat of arms of Diest") [Diest](/in/diest/design "English jobs in Diest") * 1 ![Geraardsbergen](/public/img/coa/be.geraardsbergen.png "Coat of arms of Geraardsbergen") [Geraardsbergen](/in/geraardsbergen/design "English jobs in Geraardsbergen") * 1 ![Herk-de-Stad](/public/img/coa/be.herk-de-stad.png "Coat of arms of Herk-de-Stad") [Herk-de-Stad](/in/herk-de-stad/design "English jobs in Herk-de-Stad") * 1 ![Lommel](/public/img/coa/be.lommel.png "Coat of arms of Lommel") [Lommel](/in/lommel/design "English jobs in Lommel") * 1 ![Mortsel](/public/img/coa/be.mortsel.png "Coat of arms of Mortsel") [Mortsel](/in/mortsel/design "English jobs in Mortsel") * 1 ![Ninove](/public/img/coa/be.ninove.png "Coat of arms of Ninove") [Ninove](/in/ninove/design "English jobs in Ninove") * 1 ![Rixensart](/public/img/coa/be.rixensart.png "Coat of arms of Rixensart") [Rixensart](/in/rixensart/design "English jobs in Rixensart") * 1 ![Tienen](/public/img/coa/be.tienen.png "Coat of arms of Tienen") [Tienen](/in/tienen/design "English jobs in Tienen") * 1 ![Vilvoorde](/public/img/coa/be.vilvoorde.png "Coat of arms of Vilvoorde") [Vilvoorde](/in/vilvoorde/design "English jobs in Vilvoorde") #### design in Provinces... * 517 ![Brussels](/public/img/coa/be.brussels.png "Coat of arms of Brussels") [Brussels](/in/brussels/design "English jobs in Brussels") * 395 ![West Flanders](/public/img/coa/be.west-vlaanderen.png "Coat of arms of West Flanders") [West Flanders](/in/west-vlaanderen/design "English jobs in West Flanders") * 324 ![East Flanders](/public/img/coa/be.oost-vlaanderen.png "Coat of arms of East Flanders") [East Flanders](/in/oost-vlaanderen/design "English jobs in East Flanders") * 322 ![Antwerp Province](/public/img/coa/be.antwerpen-province.png "Coat of arms of Antwerp Province") [Antwerp Province](/in/antwerpen-province/design "English jobs in Antwerp Province") * 249 ![Hainaut](/public/img/coa/be.hainaut.png "Coat of arms of Hainaut") [Hainaut](/in/hainaut/design "English jobs in Hainaut") * 214 ![Flemish Brabant](/public/img/coa/be.vlaams-brabant.png "Coat of arms of Flemish Brabant") [Flemish Brabant](/in/vlaams-brabant/design "English jobs in Flemish Brabant") * 184 ![Walloon Brabant](/public/img/coa/be.brabant-wallon.png "Coat of arms of Walloon Brabant") [Walloon Brabant](/in/brabant-wallon/design "English jobs in Walloon Brabant") * 90 ![Limburg](/public/img/coa/be.limburg.png "Coat of arms of Limburg") [Limburg](/in/limburg/design "English jobs in Limburg") * 66 ![Liège Province](/public/img/coa/be.liege-province.png "Coat of arms of Liège Province") [Liège Province](/in/liege-province/design "English jobs in Liège Province") * 55 ![Namur Province](/public/img/coa/be.namur-province.png "Coat of arms of Namur Province") [Namur Province](/in/namur-province/design "English jobs in Namur Province") * 46 ![Belgian Luxembourg](/public/img/coa/be.luxembourg.png "Coat of arms of Belgian Luxembourg") [Belgian Luxembourg](/in/luxembourg/design "English jobs in Belgian Luxembourg") ## Select languages you speak Save & Close Cancel IN OTHER COUNTRIES * [Austria](https://englishjobsearch.at) * [Switzerland](https://englishjobsearch.ch) * [Germany](https://englishjobs.de) * [Denmark](https://englishjobs.dk) * [Spain](https://englishjobs.es) * [Finland](https://englishjobs.fi) * [France](https://englishjobs.fr) * [Italy](https://englishjobs.it) * [Luxembourg](https://englishjobs.lu) * [Netherlands](https://englishjobsearch.nl) * [Norway](https://englishjobs.no) * [Poland](https://englishjobs.pl) * [Portugal](https://englishjobs.pt) * [Sweden](https://englishjobsearch.se) ABOUT * [FAQ](/faq) * [For Employers](https://englishjobs.com) * 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